Resistive Memory Structure with Buffer Layer

ABSTRACT

A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

CROSS-REFERENCE TO OTHER APPLICATIONS

The present application is a continuation of U.S. patent applicationSer. No. 12/836,304, filed on 14 Jul. 2010, Attorney Docket MXIC 1845-2;which application is a continuation of U.S. patent application Ser. No.12/176,183, filed on 18 Jul. 2008, now U.S. Pat. No. 7,777,215, AttorneyDocket MXIC 1845-1; which application claims the benefit of U.S.Provisional Patent Application No. 60/950,874, filed on 20 Jul. 2007,Attorney Docket MXIC 1845-0.

The present application is related to the following U.S. patentapplications: Resistance Random Access Memory Structure for EnhancedRetention, U.S. patent application Ser. No. 11/560,723, filed on 16 Nov.2006, published on 22 May 2008 as publication number US-2008-0116440-A1,Attorney Docket MXIC 1741-1; and Resistance Memory with TungstenCompound and Manufacturing, U.S. patent application Ser. No. 11/955,137,filed on 12 Dec. 2007, published on 11 Dec. 2008 as publication numberUS-2008-0304312-A1, Attorney Docket MXIC 1742-2.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to memory devices and methods formanufacturing high density memory devices, and more particularly tomemory devices having a data storage material based on tungsten-oxygencompounds.

2. Description of Related Art

Nonvolatile memory devices include magnetic random access memory MRAM,ferroelectric random access memory FRAM and phase-change random accessmemory PCRAM and other resistive random access memory RRAM. RRAM hasattracted much attention because of its simple structure and small cellsize.

Metal-oxide based RRAM can be caused to change resistance between two ormore stable ranges by application of electrical pulses at levelssuitable for implementation in integrated circuits, and the resistancecan be read and written with random access to indicate stored data.

NiO, TiO₂, HfO₂, and ZrO₂ based RRAM have been investigated for use as amemory material in memory cells. See, Baek, et al., “Highly ScalableNon-Volatile Resistive Memory using Simple Binary Oxide Driven byAsymmetric Unipolar Voltage Pulses”, IEDM Technical Digest pp.23.6.1-23.6.4, IEEE International Electron Devices Meeting 2004. Thesememory cells are formed by a non-self-aligned process in a M-I-Mstructure, where M is a noble metal acting as an electrode and I is oneof NiO, TiO₂, HfO₂, and ZrO₂. This MIM structure requires severaladditional masks and patterning to form the noble metal electrodes andthe memory material, and results in a relatively large memory cell size.

Cu_(x)O based RRAM has also been investigated for use as a memorymaterial in memory cells. See, Chen et al., “Non-Volatile ResistiveSwitching for Advanced Memory Applications”, IEDM Technical Digest pp.746-749, IEEE International Electron Devices Meeting 2005. The Cu_(x)Omaterial is formed by thermal oxidation of a copper via which acts asthe bottom electrode for the memory cell, while the top electrodeconsists of a bi-layer Ti/TiN film that is deposited and etched. Thisstructure requires several additional masks to form the top and bottomelectrodes, and results in a relatively large memory cell size. Chen etal. disclose that having a copper bottom electrode complicates erasingof the memory cell since the applied field during erasing may pushcopper ions into the Cu_(x)O. Additionally, Cu_(x)O has a relativelysmall resistance window of 10×.

Cu—WO₃ based RRAM has also been investigated for use as a memorymaterial in memory cells. See, Kozicki et al., “A Low-Power NonvolatileSwitching Element Based on Copper-Tungsten Oxide Solid Electrolyte”,IEEE Transactions on Nanotechnology pp. 535-544, Vol. 5, No. 5,September 2006. Switching elements fabricated using tungsten metal, asolid electrolyte based on tungsten-oxide and photodiffused copper, anda copper top electrode are disclosed. The switching element is formed bytungsten-oxide grown or deposited on tungsten material, a layer of Cuformed on the tungsten-oxide and the Cu photodiffused into thetungsten-oxide to form the solid electrolyte, and a Cu layer is formedand patterned over the solid electrolyte to act as a top electrode. Theswitching element changes resistance by applying a bias voltage to causeelectrodeposition of Cu ions from the top electrode into the solidelectrolyte, and states that “a lack of Cu in the top electrode resultsin no measurable switching activity” (see page 539, column 1). Thisstructure thus needs a Cu top electrode, involves several process stepsto form the solid electrolyte, and necessitates bias voltages ofopposite polarities to cause the injection of Cu ions to program anderase the solid electrolyte.

SUMMARY OF THE INVENTION

An example of a memory device comprises first and second electrodes witha memory element and a buffer layer located between and electricallycoupled to the first and second electrodes. The memory element comprisesone or more metal oxygen compounds. The buffer layer comprises at leastone of an oxide and a nitride. In some example is the buffer layer has athickness of less than 50 Å. In some example is the memory elementcomprises one or more tungsten oxygen compounds. In some examples thebuffer layer comprises at least one of the following: SiO₂, WO, TiO,NiO, AlO, CuO, ZrO, Si₃N₄, and TiN. In some examples memory elementcomprises one or more of the following: WOx, NiO, Nb₂O₅, CuO₂, Ta₂O₅,Al₂O₃, CoO, Fe₂O₃, HfO₂, TiO₂, SrTiO₃, SrZrO₃, (BaSr)TiO₃, GeTi, SnMnTe,SbTe, Pr1-xCaxMnO₃, (Te—Cu/GdOX, GeSb with Ag⁺ or Cu⁺).

A second example of a memory device comprises a first electrode and asecond electrode with a memory element and a buffer layer locatedbetween and electrically coupled to the first and the second electrodes.The memory comprises one or more metal oxygen compounds. The bufferlayer has a thickness of less than 50 Å.

An example of a method of fabricating a memory device is carried out asfollows. A first electrode and a second electrode are formed. A memory,located between and electrically coupled to the first and the secondelectrodes, is formed; the memory comprises one or more metal oxygencompounds and the buffer layer comprises at least one of an oxide and anitride. In some examples the buffer layer is located between andelectrically coupled to the memory element and the first electrode. Insome examples the buffer layer has a thickness of less than 50 Å. Insome examples the buffer layer has a resistivity of about 10¹³˜10¹⁶ohm-cm. In some examples a second buffer layer is formed between andelectrically coupled to the memory element and the second electrode, thesecond buffer layer comprising at least one of an oxide and a nitride.

Advantageously, the present invention improves the performance,including data retention and cycle endurance, of a resistive memorystructure.

The structures and methods of the present invention are disclosed in thedetailed description below. This summary does not purport to define theinvention. The invention is defined by the claims. These and otherembodiments, features, aspects, and advantages of the technology can beunderstood with regard to the following description, appended claims andaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with respect to specific embodimentsthereof, and reference will be made to the drawings, in which:

FIG. 1 is a simplified cross-sectional view of an example of a resistivememory structure in accordance with the present invention with a barrierlayer between the bottom electrode and the memory cell.

FIG. 2 is a simplified cross-sectional view of another example of aresistive memory structure similar to that of FIG. 1 but where thebuffer layer is between the memory cell and the top electrode.

FIG. 3 is a simplified cross-sectional view of a further example of aresistive memory structure similar to that of FIG. 1 including a bufferlayer between the bottom electrode and the memory cell as in FIG. 1 anda buffer layer between the top electrode and the memory cell as in FIG.2.

FIG. 4 is a graph of resistivity versus retention time for a resistivememory structure of the type not including a buffer layer.

FIG. 5 is a graph of resistivity versus retention time for a resistivememory structure made according to the invention showing the improveddata retention over the data retention illustrated in FIG. 4.

FIG. 6 is a graph of resistivity versus cycle time for a memorystructure of the type not including a buffer layer.

FIG. 7 is a graph of resistivity versus cycle time for a resistivememory structure made according to the invention showing the improvedcycle endurance over the cycle endurance illustrated in FIG. 6.

FIG. 8 is a graph of resistivity versus read disturb for a resistivememory structure made according to the invention showing that itexhibits very good read disturb characteristics in both the on state andthe off state.

FIG. 9 is a simplified block diagram of an integrated circuit includingresistive memory structures.

DETAILED DESCRIPTION

A description of structural embodiments and methods of the presentinvention is provided with reference to FIGS. 1-9. It is to beunderstood that there is no intention to limit the invention to thespecifically disclosed embodiments but that the invention may bepracticed using other features, elements, methods and embodiments. Likeelements in various embodiments are commonly referred to with likereference numerals.

FIG. 1 is a simplified cross-sectional view of a first example of aresistive memory structure 10. Structure 10 includes a substrate 11 uponwhich an AlCu stack 12 is formed. A dielectric layer 14, typicallysilicon dioxide, is formed over stack 12. A bottom electrode 16 extendsfrom stack 12 completely through dielectric layer 14. Bottom electrode16 is an electrically conductive element. For example, bottom electrode16 may be a drain terminal of an access transistor or a terminal of adiode. A buffer layer 18 is formed by, for example, down-stream plasma,plasma sputtering or reactive sputtering onto dielectric layer 14 andbottom electrode 16. Buffer layer 18 has a thickness of less than 50 Å;the advantages accruing from the use of buffer layer 18 will bediscussed below. Buffer layer 18 comprises at least one of an oxide anda nitride. For example, buffer layer 18 may comprise at least one of thefollowing: SiO₂, WO, TiO, NiO, AlO, CuO, ZrO, Si₃N₄, and TiN. Bufferlayer 18 preferably exhibits a resistivity of about 10¹³˜10¹⁶ ohm-cm andpreferably has a thickness of less than 5 nm (50 Å). Buffer layer 18 maybe formed by, for example, physical vapor deposition or chemical vapordeposition methods.

A memory element layer 20, having a thickness of 50-1000 Å, is depositedon buffer layer 18. Memory element layer 20 comprises one or moremetal-oxygen compounds, especially tungsten-oxygen compounds W_(x)O_(y),for example one or more of WO₃, W₂O₅, WO₂. In some cases, such as whenplasma oxidation or thermal oxidation is used to form memory elementlayer 20, the result can be a number of different tungsten-oxygencompounds. In one example memory element layer 20 comprises WO₃/W₂O₅/WO₂and has a thickness of about 140 Å. A top electrode 22 is formed onmemory element layer 20. Electrodes 16, 22 are typically a metal such astungsten or AlCu. The portions of the bottom and top electrodes 16, 22that are aligned define a memory cell region 24 therebetween. Theportion of memory element layer 20 situated within memory cell region 24constitutes a memory element 26 electrically coupled to bottom and topelectrodes 16, 22. Memory element 26 may comprise one or more of thefollowing: WO_(x), NiO, Nb₂O₅, CuO₂, Ta₂O₅, Al₂O₃, CoO, Fe₂O₃, HfO₂,TiO₂, SrTiO₃, SrZrO₃, (BaSr)TiO₃, GeTi, SnMnTe, SbTe,Pr_(1-x)Ca_(x)MnO₃, (Te—Cu/GdOX, GeSb with Ag⁺ or Cu⁺).

In operation, voltages applied to the top and bottom electrodes 22, 16will cause current to flow between the top and bottom electrodes viamemory element 26 and can induce a programmable change in electricalresistance of the memory element 26, the electrical resistanceindicating a data value stored in the memory element 26. In someembodiments memory element 26 can store two or more bits of data.

FIG. 2 is a simplified cross-sectional view of another example of aresistive memory structure 10 similar to that of FIG. 1 but withoutbuffer layer 18 but including a buffer layer 19 between memory element26 and at top electrode 22. FIG. 3 is a simplified cross-sectional viewof a further example of a resistive memory structure 10 including abuffer layer 18 between bottom electrode 16 and memory element 26 as inFIG. 1 and a buffer layer 19 between top electrode 22 and the memoryelement 26 as in FIG. 2.

Resistive memory structure 10 can be manufactured using conventionalback-end-of-line W-plug processing techniques. A single mask can be usedto form both buffer layer 19 and top electrode 22.

The use of one or both of buffer layers 18, 19 helps to improve theperformance of resistive memory structure 10. This improvement inperformance will be demonstrated with reference to FIGS. 4-8. Thestructure of FIG. 1 was used to develop the results seen at FIGS. 5, 7and 8. The test structure had the following characteristics: bottomelectrode 16 was made of W and had an average diameter of about 200 nm;top electrode 22 was made of Al and had an average width of about 500nm; memory element layer 20 was made of WO_(x) and a thickness of about140 Å; buffer layer 18 was made of SiO₂ and had a thickness of about 2nm. The results shown at FIGS. 4 and 6 are for a resistive memorystructure substantially identical to the test structure but without anybuffer layers, referred to below as the conventional resistive memorystructure.

FIG. 4 is a graph of resistivity versus retention time for theconventional resistive memory structure in both the on state and the offstate. It can be seen that the resistivity, especially in the on state,increases relatively quickly over time, time being plotted on alogarithmic scale. In contrast, the plot of resistivity versus retentiontime for resistive memory structure 10 is seen in FIG. 5 to beessentially flat, a substantial improvement over the conventionalresistive memory structure used to create the graph of FIG. 4.

FIG. 6 is a graph of resistivity versus cycle time for the conventionalresistive memory structure. Graphs for both the on state and the offstate show significant increases in the resistivity over cycle time. Incontrast, the graph of FIG. 7 of resistivity versus cycle time forresistive memory structure 10 shows a relatively flat resistivity versuscycle time plots for both the on state and the off state. This indicatessubstantially improved cycle endurance for resistive memory structure 10over the cycle endurance of the conventional resistive memory structureused to create the graph in FIG. 6.

FIG. 8 is a graph of resistivity versus read disturb for resistivememory structure 10 showing that the resistivity of structure 10exhibits very good read disturb characteristics in both the on state andthe off state. Read disturb refers to the gain or loss of resistance ofmemory element 26 resulting from reading the state of the memory element26.

FIG. 9 is a simplified block diagram of an integrated circuit 110including a memory array 112 implemented using resistive memorystructures 10. A word line decoder 114 having read, set and reset modesis coupled to and in electrical communication with a plurality of wordlines 116 arranged along rows in the memory array 112. A bit line(column) decoder 118 is in electrical communication with a plurality ofbit lines 120 arranged along columns in the array 112 for reading,setting, and resetting memory element 26 in array 112. Addresses aresupplied on bus 122 to word line decoder and drivers 114 and bit linedecoder 118. Sense amplifiers and data-in structures in block 124,including voltage and/or current sources for the read, set, and resetmodes are coupled to bit line decoder 118 via data bus 126. Data issupplied via a data-in line 128 from input/output ports on integratedcircuit 110, or from other data sources internal or external tointegrated circuit 110, to data-in structures in block 124. Othercircuitry 130 may be included on integrated circuit 110, such as ageneral purpose processor or special purpose application circuitry, or acombination of modules providing system-on-a-chip functionalitysupported by array 112. Data is supplied via a data-out line 132 fromthe sense amplifiers in block 124 to input/output ports on integratedcircuit 110, or to other data destinations internal or external tointegrated circuit 110.

A controller 134 implemented in this example, using a bias arrangementstate machine, controls the application of bias arrangement supplyvoltages and current sources 136, such as read, program, erase, eraseverify and program verify voltages and/or currents. Controller 134 maybe implemented using special-purpose logic circuitry as known in theart. In alternative embodiments, controller 134 comprises ageneral-purpose processor, which may be implemented on the sameintegrated circuit to execute a computer program to control theoperations of the device. In yet other embodiments, a combination ofspecial-purpose logic circuitry and a general-purpose processor may beutilized for implementation of controller 134.

An exemplary formation method for W_(x)O_(y) uses a PVD sputtering ormagnetron-sputtering method with reactive gases of Ar, N₂, O₂, and/orHe, etc. at a pressure of 1 mTorr˜100 mTorr, using a target ofW_(x)O_(y). The deposition is usually performed at room temperature. Acollimater with an aspect ratio of 1˜5 can be used to improve thefill-in performance. To improve the fill-in performance, the DC bias ofseveral tens of volts to several hundreds of volts is also used. Ifdesired, DC bias and the collimater can be used simultaneously.

A post-deposition annealing treatment in vacuum or in an N₂ ambient orO₂/N₂ mixed ambient is optionally performed to improve the oxygendistribution of metal oxide. The annealing temperature ranges from 400°C. to 600° C. with an annealing time of less than 2 hours.

Yet another formation method uses oxidation by a high temperatureoxidation system, such as a furnace or a rapid thermal pulse (“RTP”)system. The temperature ranges from 200° C. to 700° C. with pure O₂ orN₂/O₂ mixed gas at a pressure of several mTorr to 1 atm. The time canrange several minutes to hours. Another oxidation method is plasmaoxidation. An RF or a DC source plasma with pure O₂ or Ar/O₂ mixed gasor Ar/N₂/O₂ mixed gas at a pressure of 1 mTorr to 100 mTorr is used tooxidize the surface of W. The oxidation time ranges several seconds toseveral minutes. The oxidation temperature ranges from room temperatureto 300° C., depending on the degree of plasma oxidation.

The invention has been described with reference to specific exemplaryembodiments. Various modifications, adaptations, and changes may be madewithout departing from the spirit and scope of the invention.Accordingly, the specification and drawings are to be regarded asillustrative of the principles of this invention rather thanrestrictive, the invention is defined by the following appended claims.For example, a transition or protective layer of material could be usedbetween the buffer layer and one or both of the memory element and anelectrode.

Any and all patents, patent applications and printed publicationsreferred to above are incorporated by reference.

1. A method of fabricating a memory device, comprising: forming a firstelectrode and a second electrode; and forming a memory element and abuffer layer located between and electrically coupled to the first andthe second electrodes, the memory element comprising one or more metaloxygen compounds, the buffer layer comprising at least one of an oxideand a nitride.
 2. The method according to claim 1, wherein the bufferlayer is formed by down-stream plasma, plasma sputtering or reactivesputtering.
 3. The method according to claim 1, wherein the memoryelement is formed by plasma oxidation or thermal oxidation.
 4. Themethod according to claim 1, wherein the buffer layer is located betweenand electrically coupled to the memory element and the first electrode.5. The method according to claim 1, wherein the buffer layer has athickness of less than 50 Å.
 6. The method according to claim 1, whereinthe buffer layer has a resistivity of about 10¹³˜10¹⁶ ohm-cm.
 7. Themethod according to claim 4, further comprising forming a second bufferlayer located between and electrically coupled to the memory element andthe second electrode, the second buffer layer comprising at least one ofan oxide and a nitride.
 8. The method according to claim 7, wherein thesecond buffer layer has a thickness of less than 50 Å
 9. The methodaccording to claim 1, wherein the memory element has a thickness,measured between the first and second electrodes, of 50-1000 Å.
 10. Themethod according to claim 1, wherein the memory element comprises atleast one of the following: WO_(x), NiO, Nb₂O₅, CuO₂, Ta₂O₅, Al₂O₃, CoO,Fe₂O₃, HfO₂, TiO₂, SrTiO₃, SrZrO₃, (BaSr)TiO₃, GeTi, SnMnTe, SbTe,Pr_(1-x)Ca_(x)MnO₃, (Te—Cu/GdOX, GeSb with Ag⁺ or Cu⁺).
 11. The methodaccording to claim 1, wherein the buffer layer comprises at least one ofthe following: a tungsten oxide, a titanium oxide, an aluminum oxide, azirconium oxide and a silicon nitride.
 12. The method according to claim1, wherein the buffer layer comprises SiO₂.
 13. A method for fabricatinga memory device comprising: forming a first electrode and a secondelectrode; forming a memory element and a buffer layer located betweenand electrically coupled to the first and the second electrodes;selecting the memory element to comprise at least one of the following:WO_(x), NiO, Nb₂O₅, CuO₂, Ta₂O₅, Al₂O₃, CoO, Fe₂O₃, HfO₂, TiO₂, GeTi,SnMnTe, SbTe, Pr_(1-x)Ca_(x)MnO₃, (Te—Cu/GdOX, GeSb with Ag⁺ or Cu)⁺;and selecting the buffer layer to comprise at least one of thefollowing: a tungsten oxide, a titanium oxide, an aluminum oxide, azirconium oxide and a silicon nitride.
 14. The method according to claim13, wherein the buffer layer is located between and electrically coupledto the memory element and the first electrode.
 15. The method accordingto claim 14, further comprising a second buffer layer located betweenand electrically coupled to the memory element and the second electrode,the second buffer layer comprising at least one of an oxide and anitride.
 16. The memory device according to claim 13, wherein the memoryelement is a programmable resistance memory element.
 17. A method offabricating a memory device comprising: forming a first electrode;forming a metal oxide resistive random access memory element locatedover and electrically coupled to the first electrode; the memory elementcomprising at least one of the following: WO_(x), NiO, Nb₂O₅, CuO₂,Ta₂O₅, Al₂O₃, CoO, Fe₂O₃, HfO₂, TiO₂, Pr_(1-x)Ca_(x)MnO₃, (Te—Cu/GdOX,GeSb with Ag⁺ or Cu⁺); forming a buffer layer located over andelectrically coupled to the memory element; and forming a secondelectrode located over and contacting the buffer layer.
 18. The methodaccording to claim 17, wherein the buffer layer has a resistivity ofabout 10¹³˜10¹⁶ ohm-cm.
 19. The method according to claim 17, furthercomprising forming a second buffer layer located between andelectrically coupled to the memory element and the first electrode, thesecond buffer layer comprising at least one of an oxide and a nitride.20. The method according to claim 19, wherein the second buffer layerhas a thickness of less than 50 Å.
 21. The method according to claim 17,wherein the memory element has a thickness, measured between the firstand second electrodes, of 50-1000 Å.
 22. The method according to claim17, further comprising selecting the buffer layer to comprise at leastone of the following: a tungsten oxide, a titanium oxide, an aluminumoxide, a zirconium oxide, a silicon nitride and a titanium nitride. 23.The method according to claim 17, further comprising selecting thebuffer layer to comprise SiO₂.
 24. The method according to claim 17,wherein the memory element is a programmable resistance random accessmemory element.